Key Persons

Queen’s University Belfast – Project Coordinator

Dr. Georgios Karakonstantis (M) is a lecturer in the School of Electronics, Electrical Engineering and Computer Science of the Queen’s University, Belfast and a member of the Data Science and Scalable Computing Research Centre of the ECIT Institute. Prior to joining Queen’s, Georgios was a senior research scientist at the Swiss Federal Institute of Technology in Lausanne (EPFL), Switzerland. He received his Ph.D. degree from the Electrical and Computer Engineering department of the Purdue University, U.S.A, in 2010. In the summer of 2008, he was with the Advanced Technology Group, Qualcomm Inc., San Diego, CA, and in 2003 he worked in the VLSI lab of Intracom, Athens, Greece. He has authored over 50 papers in referred journals and conferences, a patent and a book chapter. In 2012 he was awarded a 4-year Marie-Curie Career Integration Grant by the European Commission and in 2010, his work on a quality adaptive and energy efficient camera was recognised at the International Altera Innovate Design Contest. Georgios has setup and led 5 European, Swiss and industrial funded projects as investigator on the design of energy efficient and error resilient computing systems.

Prof. Dimitrios S. Nikolopoulos (M) (FBCS, SMIEEE, SMACM, pubs=149, h-index=24) is Professor in the School of EEECS, at Queen’s University of Belfast, where he is also Research Director in High Performance and Distributed Computing. His current research activity explores co-designed hardware and software for high performance computing and new computing paradigms at the limits of power and reliability. Professor Nikolopoulos is known for research contributions to system software for many-core distributed and embedded systems. These contributions have not only improved the efficiency and sustainability of supercomputers, but also made these supercomputers easy to use by non-experts. Many of his contributions evolved into commercial products or open tools for scientists and engineers. The accolades of Dimitrios include the NSF CAREER Award, US DoE Early Career Principal Investigator Award, IBM Faculty Award, Marie Curie, HiPEAC Fellowship and seven best paper awards from top-tier conference such as SC and PPoPP. His research has been supported with over £23 million of highly competitive, external research funding. Professor Nikolopoulos is the Coordinator of the NanoStreams (FP7-610509, €3.3m), ALEA (EP/L000055/1, £700k) and SERT (EP/M01147X/1, £1m), three major collaborative efforts in the EU and the UK that explore disruptive software and hardware technologies for improving the energy-efficiency of many-core computing systems at scale. Professor Nikolopoulos is a Fellow of the British Computer Society, Senior Member of the IEEE, and Senior Member of the ACM. He is an Associate Editor of the International Journal of High Performance Computing Applications. He has served as Program Co-Chair of four flagship IEEE and ACM conferences (SC, CCGrid, IPDPS, ICPP), General Chair of the IEEE Cluster Computing Conference, and Program Committee Member for over 100 more ACM and IEEE conferences. He also serves regularly as grant proposal review panellist for EPSRC (UK), NSF (US), and NSERC (Canada). He earned BEng (’96), MEng (’97) and PhD (’00) degrees from the University of Patras.

Professor Maire O’Neil (F) is currently Director of Research for Data Security Systems at the Centre for Secure Information Technologies (CSIT), Queen’s University Belfast. She holds a prestigious 5-year £1.2M EPSRC Leadership Fellowship and was a former holder of a Royal Academy of Engineering research fellowship. She has received numerous awards for her research which include British Female Inventor of the Year 2007 and the Women’s Engineering Society (WES) prize at the 2006 IET Young Woman Engineer of the Year event. She has authored a research book on symmetric-key cryptographic architectures and has over 115 peer-reviewed conference and journal publications. She was guest editor of the launch issue of IET Information Security in 2005 and is currently on the editorial board of the International Journal of Reconfigurable Computing. She has given numerous invited talks and has been a technical program committee member for many international conferences, including DAC, CHES, DATE, SOCC, ISCAS, and IET ISSC. She is an IEEE Circuits & Systems for Communications (CASCOM) Technical committee member and acted as treasurer of the Executive Committee of the IEEE United Kingdom and Ireland (UKRI) Section, 2008-2010. She is a fellow of the HEA and a member of the IET, IEEE and the International Association for Cryptologic Research (IACR).

Dr. Hans Vandierendonck (M) is Lecturer at Queen’s University of Belfast. His research area is situated around the design and performance of high-performance computer systems. His research has contributed to the design of runtime systems for task data-flow parallel programming models and to the design of programmer-assisted parallelization through a combination of dynamic analysis and automatic parallelizing compilers. He obtained the MSc in Computer Science at Ghent University, Belgium in 1999 and the PhD degree at Ghent University in 2004. He was Fellow with the Research Foundation Flanders (FWO) from October 2004 until March 2012. He received the Jozef Plateau Prize from the Alumni Association of Engineers at Ghent University for his MSc Thesis (2000), and the IBM Belgium Prize for Informatics twice, once for his MSc Thesis (2000) and once for his PhD thesis (2004). He was visiting researcher at Universidat Polytecnica de Catalunya with Prof. Mateo Valero for 3 months in 2001, at INRIA Rennes with Prof. André Seznec for 3 months in 2005 as well as at the Foundation of Research and Technology Hellas (FORTH) with Prof. Dimitrios S. Nikolopoulos for 12 months in 2010-2011. He is member of the IEEE and of the ACM.

University of Cyprus

Dr. Yiannakis Sazeides (M) is an Associate Professor in the Department of Computer Science at the University of Cyprus since 2000. He was awarded a PhD degree in 1999 from the University of Wisconsin, Madison. He worked in research labs for the development and design of high performance processors with Compaq in 1999 and Intel in 2001 and 2002. He did a HiPEAC sponsored mini-sabbatical at ARM in 2011 exploring the convergence of reliability and security. He was the leader of the Task Force on Reliability and Availability in FP7 HiPEAC2 Network of Excellence and is currently in the advisory board of HiPEAC3. He is actively contributing in the organization of many workshops related to fault-tolerance. He was also responsible for the organization of the HiPEAC 2009 conference in Cyprus and the tutorials and workshops chair of ISCA2010. He serves regularly in Program Committees of several international conferences (such as ISCA, MICRO and HPCA). His research interests lie in the area of Computer Architecture with particular emphasis in fault-tolerance, data-centre modelling, memory hierarchy and dynamic program behavior. In the FP7 EuroCloud project he was leading the work related to reliability and TCO (total-cost-of-ownership) modelling of data-centres. In the currently running FP7 HAPRA project he is leading the effort related to monitors and knobs for harnessing performance variability due to time-dependent aging of processors for both general purpose and embedded processors. He has over 60 publications including two patents.

Dr. Pedro Trancoso (M) is an Associate Professor at the Department of Computer Science at the University of Cyprus, which he joined in 2002. He has a PhD from the University of Illinois at Urbana-Champaign, USA. He serves as Co-Editor for the IEEE Computing in Science & Engineering for the Novel Architectures Department and has been General Chair and Program Co-Chair for the ACM Conference on Computing Frontiers in 2012 and 2011, respectively. He has also been the Co-Organizer of the Error-Aware Systems Thematic Session at the HiPEAC CSW event in Athens in 2014. In addition, he participated in the Program Committee of several major International Conferences (e.g. ISCA and PACT) and serves as reviewer for major journals. His research interests are in the area of Computer Architecture and include Multi-core Architectures, Memory Hierarchy, Intelligent Memory, Parallel Processing and Programming Models, Database Workloads, High-Performance Computing, Approximate Computing and Energy Efficiency. He has published more than 70 articles in both journals and conference proceedings. He has supervised 4 PhD dissertations and 5 MSc theses. The PhD alumni held positions at major institutions such as the Intel Labs Barcelona (Spain) and Imagination Technologies (UK). Currently his research team, Computer Architecture, Systems and Performance Evaluation Research – CASPER ( is composed of 2 PhD students, 1 MSc student, and 3 undergraduate students. A team formed out of three of his students has achieved the third position in the IEEEXtreme 2007 and 2006 International Competition organized by IEEE. Three of his students have received the first prize for Best Undergraduate Research Project from the Cypriot Research Promotion Foundation for their final-year projects done under his supervision. The latest funding for his research include the participation in the TERAFLUX EU FP7 IP project (4 years, EUR7.5mil total budget) and the lending of a 48-core experimental processor, the Intel SCC, by the Intel Corporation. He is also a member of the HiPEAC Network of Excellence.

University of Athens

Prof. Dimitris Gizopoulos (M) is professor at the Department of Informatics & Telecommunications, of National and Kapodistrian University of Athens where he leads the Computer Architecture Laboratory since 2011. Previously, he led for ten years the Computer System Laboratory of the University of Piraeus. His research focuses on the dependability, performance and power of computer architectures. Gizopoulos has published more than 130 papers in peer reviewed IEEE and ACM journals and conferences, is an inventor of five US patents, author a book and editor of a second on testing and fault tolerance. He is associate editor of IEEE Transactions on Computers, IEEE Transactions on VLSI Systems, and IEEE Design & Test of Computers Magazine. He served several times as member of the Steering, Organizing and Program Committees, and as General and Program Chair of major IEEE and ACM conferences. He is an IEEE Fellow and a Golden Core Member of IEEE Computer Society. He participated in and led several research and development projects funded by the EU, the Greek government and private funds from companies. Gizopoulos is the UoA lead in the CLERECO FP7 project, and also the coordinator of the HOLISTIC and DIaSTEMA projects (both funded by EU and the Greek government), a member of HiPEAC NoE and the Vice-chair of the MEDIAN ESF-funded COST Action.

Prof. Antonis Paschalis (M) is professor at the Department of Informatics & Telecommunications, of National and Kapodistrian University of Athens. His research interests are space electronics design and fault tolerance, embedded processor-based self-test, fault tolerant design and architecture. Antonis has published more than 130 papers in peer-reviewed transactions, journals, and conferences. He has been involved in projects funded by the EU and the Greek government and currently leads UoA participation in ESA’s PROBA3 mission. He was member of the editorial board of Journal of Electronic Testing: Theory and Applications and served as member of organizing and program committees of international events (DATE, VTS, ETS, IOLTS, DFTS, etc.) and as General Chair of IOLTS and ETW. He is a member of the IEEE and Golden Core member of IEEE Computer Society.

AMCC Deutschland GmbH

Greg Favor is Chief Architect and VP of Processor Development at APM. He received a BS in CS/EE from Caltech (California Institute of Technology) in 1983. He has been responsible for a number of high-performance processor designs through the 32-bit and 64-bit generations of architectures, including the AMD K6 family of x86 processors in the 90’s, the Redback/Ericsson packet processor architecture in the 2000’s, and the X-Gene family of 64-bit ARM v8-A processors presently. X-Gene 1 was the very first implementation of the new ARM v8-A architecture; X-Gene 2 has built upon that, including the addition of full hardware IO virtualization and RDMA (RoCE) to support the creation of efficient scale-out systems.

Kumar Sankaran is the Associate Vice President of Software and Platform Engineering at Applied Micro. He is responsible for the software architecture and development and platform engineering for the X-Gene family of products from Applied Micro. In addition, he handles the software eco-system development and promotion within the ARM64 community. Kumar has been a member of the technical steering committee with the Linaro Enterprise Group (LEG) which is responsible for the software standards and definitions for all ARM64 servers. Kumar has a Bachelor of Engineering degree in Electronics Engineering, a Master of Science degree in Computer Science and an MBA in Marketing/Finance. He joined Applied Micro in 2010


Dr. Shidhartha Das (M) is a Principal Engineer working for ARM Ltd., UK in the research and development division. He received the B.Tech degree in electrical engineering from the Indian Institute of Technology, Bombay in 2002 and the M.S and Ph.D degrees in computer science and engineering from the University of Michigan, Ann Arbor in 2005 and 2009.His research interests include micro-architectural and circuit design for variation measurement and mitigation, on-chip power delivery and VLSI architectures for digital signal processing (DSP) accelerators. His research has been featured in IEEE Spectrum and has won several awards including the Microprocessor Review analysts’ choice award in innovation and best paper awards at MICRO 2003 and SAME 2010. He has authored more than 25 papers in peer-reviewed journals and conferences, including invited publications in top-tier journals. Dr. Das works on several aspects of low-power, variation-tolerant circuits and micro-architectural design. Dr. Das serves on the Technical Program Committee of the European Solid-State Circuits Conference (ESSCIRC), International Symposium on Low-Power Engineering and Design (ISLPED) and the International On-Line Testing Symposium.

IBM Ireland Ltd

Dr. M. Mustafa Rafique (M) is a Research Scientists in the High Performance Systems team at IBM Research in Ireland. His research focus on HPC, computational accelerator-based computing, and cloud infrastructures. His research explores the design, development, and evaluation of large-scale, parallel and distributed computing systems comprising heterogeneous architectures. He graduated with a Ph.D. in computer science from Virginia Tech in 2011, and has published over 25 peer-reviewed papers in the leading conferences and journals of his field.
Dr. Kostas Katrinis (M) is a Research Staff Member and Manager in IBM Research – Ireland, heading the High Performance Systems Department. His latest research and innovation work has focused on novel workload-aware data-centre interconnect architectures and vertical workload characterization/orchestration. In the past, he has taken on challenges in systems networking and networking design challenges, including execution of European and national projects. A Fulbright Foundation and Marie Curie Fellowship nominee, Dr. Katrinis is co-author of more than 45 world-class scientific publications and co-inventor in numerous patents. He holds a Ph.D. degree from ETH Zurich, Switzerland (2006) and a BEng from the University of Patras, Greece (2000).
Dr. Pierre Lemarinier (M) is a Research Scientist in IBM Research – Ireland. He is a former Research Associate in the Distributed Computing group of the Innovative Computing Laboratory, University of Tennessee. He is currently applying parallel/distributed computing concepts and techniques to efficiently data storing, querying and staging in data-intensive computations, as well as its ramifications to resource management. In the past, Pierre worked on fault tolerance protocols for MPI libraries and their runtime environments. Dr. Lemarinier holds a Ph.D. from Universite Paris Sud, France and has numerous publications in peer reviewed scientific journals and conferencesb>

University of Thessaly

Prof. Christos D. Antonopoulos, (Male, PhD 2004), is Assistant Professor at the Electrical and Computer Engineering Department of the University of Thessaly in Volos, Greece. He earned his PhD (2004), MSc (2001) and Diploma (1998) from the Computer Engineering and Informatics Department of the University of Patras, Greece. His research interests span the areas of system and applications software for high performance computing, emphasizing on monitoring and adaptivity with performance and power/performance/quality criteria. He is the author of more than 45 refereed technical papers, has been awarded two best-paper awards in the IWOMP ’05 and PPoPP ’07 conferences, and has served as a PC member in several highly-esteemed international scientific conferences and journals. He has been actively involved in several research projects both in the EU and in USA. He currently coordinates a national research project.

Prof. Nikolaos Bellas, (Male, PhD 1998), is Associate Professor at the Electrical and Computer Engineering Department of the University of Thessaly in Volos, Greece. His research interests include Approximate Computing, Low Power design, CAD tools for architectural synthesis, multimedia and image processing for parallel machines. He received his Diploma in Computer Engineering and Informatics from the University of Patras, Greece in 1992, and MSc and PhD in Electrical and Computer Engineering from the University of Illinois, Urbana-Champaign, in 1995 and 1998, respectively. From 1999 to 2007, he was a Principal Member of Technical Staff at Motorola Labs in the US. He was one of the architects of Falcon, an MPEG4 video decoding chip used by the first Motorola camera phone, and has worked extensively on architecting Systems On Chip for multimedia and imaging applications. He was the technical leader of the Proteus project, which he conceived and proposed as a means to precipitate embedded system development and reduce time-to-market and time-to-demonstration. He has served in numerous conference program committees, including MICRO 2007. He currently coordinates the FP7 FET-Open Project SCoRPiO on Significance-based computing. He holds 10 issued US patents.

Prof. Spyros Lalis, (Male, PhD 1994), received his Diploma and PhD in Informatics Engineering from ETHZ in Switzerland. He is Associate Professor at the Electrical and Computer Engineering Department of the University of Thessaly in Volos, Greece. His interests span runtime environments, operating systems, distributed systems, network and ubiquitous computing. Among other subjects, he has worked on dynamically reconfigurable SoCs in conjunction with support for dataflow-based executions, energy-aware agent placement and migration in WSNs, and thread migration across heterogeneous embedded cores. He has published over 60 papers. He was actively involved in the technical management and implementation of several EU projects, and has coordinated a FET project.

World Sensing

Dr. Ignasi Vilajosana (M): is the CEO of Worldsensing, a company specializing in state-of-the-art industrial wireless sensor networking solutions. Prior to Worldsensing, he obtained a PhD in Physics in 2008. During his academic life he was author of more than 30 high impact publications in the geophysical and instrumentation fields. He also holds a part time professorship at the Politechnical University of Catalonia (UPC). Recently he has received appropriate business training to lead Worldsensing’s commercial activities.

Dr. Xavier Vilajosana (M): is an Associate Professor at the Universitat Oberta de Catalunya (UOC) in the area of computer networks and distributed systems. He is also Chief Innovations Officer and co-founder of Worldsensing. From 2012 to 2014 Xavier was Fullbright Visiting professor at the University of California, Berkeley. In 2009 Xavier received his PhD in Computer Sciences from the UOC. He has actively contributed to the IETF 6TiSCH working groups, he is authors of several standard proposals and RFCs at the IETF, holds 8 patents and more than 25 high impact journal publications.

Dr. Francisco Hernandez-Ramirez (M): is Project Manager in Worldsensing. He is author of more than 40 publications in peer-reviewed publications and has a long experience in National and FP7 projects.

Meritorious Audit Ltd

Panayiotis Omirou (M) received his Bachelor of Science degree (2006) in Computer Science from the Frederic Institute of Technology of Cyprus and his Master (2007) degree in Internet Technologies at the University of Bristol, Faculty of Engineering, Dept. of Computer Science. His Msc dissertation was focused on the area of 3-D web environments (“Human-Web Interaction Cycle Transition: From Flat to 3-D”). Panayiotis has worked for C.P. Palema LTD for 1 year as the IT Manager of the Company. Furthermore, he has worked at Primetel PLC for 5 years as a Senior Systems Administrator as well as the Enterprise IT Project Leader of the Company. Currently, Panayiotis is working for the Meritorius Audit Ltd as the Head of Information Technology Development Department.

Dr. Marios Kleanthous (M) received his Bachelor degree (2004) in Informatics and Telecommunications from the National and Kapodistrian University of Athens and his Master (2006) and PhD (2012) degree in Computer Science at the University of Cyprus. His PhD was in the area of Computer Architecture and more specifically in on-chip cache compression. He has been a researcher at the Department of Computer Science, in the University of Cyprus, since 2004 and continues to collaborate with the Computer Architecture group until today. In 2006 he was awarded a HiPEAC internship and he visited ARM, Cambridge, where he worked in the area of value prediction for 4 months. In 2013 he was appointed as a full time Lecturer of Computer Science at Mesoyios College and Head of the Computer Science department. In 2015 he was employed by Meritorius Audit Ltd at the position of Senior Software Engineer. His research interests are cache compression and other optimizations, 3D stacking reliability and thermal issues, and system modelling for cost, performance, reliability and Total Cost of Ownership (TCO) for datacentres. He has published 9 papers in refereed journals, conferences and workshops, and has 1 US patent. He has also served in the organizing committee of SELSE (2012 – today), and MICRO47.

Sparsity S.L.

Jordi Urmeneta Coletas (M) is an engineer with a long experience in the area of Social Analytics and mobile device hi-tech app development. He joined Sparsity in 2014 with the objective to collaborate intensively with DAMA-UPC to integrate different technologies generated by the research group in the products developed by Sparsity in order to make them more competitive using top of the line mobile graph technologies. He is participating in different FP7 projects, CoherentPaaS and SOMATCH from the FP7 and H2020 work programmes respectively.

Raquel Pau Fernández (F) has a M.Sc. in Computer Science. With more than 5 years as applications responsible for DAMA-UPC and doing her MSc and starting her PhD, she recently moved to Sparsity. She has designed, done research and implemented with her team applications in the area of social marketing (Social Media, Tweeticer, and in the software analytics of European projects (

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