WERES: Workshop on Exceeding Reliably the Energy Scaling Limits
|Date||Wednesday 27 March 2019|
|Time||8.30 – 11.30|
|Venue||Room 9 at the DATE 2019 Conference|
|DATE Session Id||CW03|
|Venue and hotels||Florence, Italy|
|Conference web site||@DATE 2019|
Conservative design margins in modern processor/memory chips may guarantee correct execution of the software layers of computing systems under various operating conditions, accounting for the inherent variability among different cores/cells of the same chip, among different manufactured chips and among different workloads; however such margins limit significantly the energy efficiency.
In this workshop, we will present recent methods and studies on design-time voltage/refresh-rate margins characterization and identification in modern multicore CPUs and DRAMs within commodity servers. In addition, we will discuss how such methods can guide informed decisions at the software layers for exceeding the conservative energy scaling limits, while presenting mechanisms at the virtualization (Hypervisor) and resource management (Openstack) layers for ensuring reliable system operation in Edge and Cloud deployments.
The talks at workshop will reveal challenges and latest results from academia and industry.
|Characterizing Power Delivery||Yiannakis Sazeides||University of Cyprus|
|Network Voltage Noise through|
|Wireless jamming detection on||Denis Guilhot||Worldsensing|
|Voltage Margins Characterization||Dimitris Gizopoulos||University of Athens|
|for Energy Efficiency in ARMv8|
|Surviving in an undervolted||Emmanouil Maroudas||University of Thessaly|
|environment: a system software|
|De-centralized resilience for||Christian Pinto||IBM Research Ireland|
|systems with non-orthodox CPU|
|Error-Resilient Memory Systems||Georgios Karakonstantis||Queen’s University Belfast|
|Exceeding the Energy Scaling|
The research presented in this workshop is supported by the Horizon 2020 UniServer project.